Product Applications

This product is primarily used in systems requiring multiple input clocks and clock synchronization.

Main Features

• Part Number: ZD701D310 / ZD701D310W
• Maximum Output Frequency:  
• LVPECL: 2.1 GHz
• LVDS: 2.1 GHz
• HCSL: 250 MHz
• LVCMOS: 250 MHz
• Power Supply Configuration: VDD/VDDO = 3.3V/3.3V or 3.3V/2.5V or 2.5V/2.5V
• Operating Temperature: -55℃ ~ 125℃
• Storage Temperature: -65℃ ~ 150℃
• Package Type: 48-pin, 7mm x 7mm WQFN
• ESD Rating: 2000V (HBM)

Feature Description

• Two pairs of universal differential input clock interfaces supporting LVPECL, LVDS, HCSL, HSTL, or single-ended clocks
• Two output banks (Bank A, Bank B), each with 5 differential output pairs, configurable as LVPECL, LVDS, HCSL, or HiZ mode
• Output Skew: 30 ps (typical, when Bank A and Bank B are configured to the same output format)
• Chip-to-Chip Output Skew: 80 ps (typical)